--Testbench zur Untersuchung der Signale der Entity "us_detection".

LIBRARY ieee ;
LIBRARY std ;
USE ieee.NUMERIC_STD.all ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_textio.all ;
USE ieee.std_logic_unsigned.all ;
USE std.textio.all ;

ENTITY usdetec_tb IS

END ;

ARCHITECTURE usdetec_tb_arch OF usdetec_tb IS

constant cf : integer := 50e6; -- 50 MHz
constant cp : time := 1000 ms / cf; -- Periode des Clocks

constant cf_lcd : integer := 400; -- 400 Hz
constant cp_lcd : time := 1000 ms / cf_lcd; -- Periode des Clocks

constant cf_us : integer := 40e3; -- 40 kHz
constant cp_us : time := 1000 ms / cf_us; -- Periode des Clocks

constant cf_us2 : integer := 360e3; -- 360 kHz
constant cp_us2 : time := 1000 ms / cf_us2; -- Periode des Clocks

constant cf_wp : integer := 15; -- 15 Hz
constant cp_wp : time := 1000 ms / cf_wp; -- Periode des Clocks


--Zeitkonstanten für die Simulation
constant t_360: time := 8333 ns; --3 / 360kHz
constant t2_360 : time := 16666 ns; --6 / 360kHz

constant t_396: time := 9166 ns; --3 / 396kHz (110%)
constant t2_396 : time := 18333 ns; --6 / 396kHz (110%)

constant t_324: time := 7500 ns; --3 / 324kHz (90%)
constant t2_324 : time := 15000 ns; --6 / 324kHz (90%)

SIGNAL clk_us_360k : STD_ULOGIC :='1' ;
SIGNAL sys_clk : STD_ULOGIC :='1' ;
SIGNAL us_switch : STD_ULOGIC :='1' ;
SIGNAL clk_400 : STD_ULOGIC :='1' ;
SIGNAL us_data : STD_ULOGIC :='0' ;
SIGNAL clk_wpm : STD_ULOGIC :='1' ;
SIGNAL us_pulses : STD_ULOGIC :='0' ;
SIGNAL clk_us_40k : STD_ULOGIC :='1' ;
SIGNAL reset : STD_ULOGIC :='1' ;

COMPONENT us_detection
PORT (
clk_us_360k : in STD_ULOGIC ;
sys_clk : in STD_ULOGIC ;
us_switch : in STD_ULOGIC ;
clk_400 : in STD_ULOGIC ;
us_data : in STD_ULOGIC ;
clk_wpm : in STD_ULOGIC ;
us_pulses : out STD_ULOGIC ;
clk_us_40k : in STD_ULOGIC ;
reset : in STD_ULOGIC );
END COMPONENT ;

BEGIN
DUT : us_detection
PORT MAP (clk_us_360k => clk_us_360k, sys_clk => sys_clk, us_switch => us_switch, clk_400 => clk_400, us_data => us_data, clk_wpm => clk_wpm, us_pulses => us_pulses, clk_us_40k => clk_us_40k, reset => reset) ;

-- Takterzeugung
sys_clk <= not sys_clk after cp / 2;
clk_400 <= not clk_400 after cp_lcd / 2;
clk_wpm <= not clk_wpm after cp_wp / 2;
clk_us_40k <= not clk_us_40k after cp_us / 2;
clk_us_360k <= not clk_us_360k after cp_us2 / 2;

 

process is
begin

-- 4 Perioden
for i in 0 to 399 loop
us_data <= '1';

wait for t_360;

us_data <= '0';

wait for t2_360;

end loop;

wait for 1 ms;

for i in 0 to 399 loop
us_data <= '1';

wait for t_396;

us_data <= '0';

wait for t2_396;

end loop;

wait for 1 ms;

for i in 0 to 399 loop
us_data <= '1';

wait for t_324;

us_data <= '0';

wait for t2_324;

end loop;

wait;
end process;

END;