--Angepasst von: https://github.com/AntonZero/WM8731-Audio-codec-on-DE10Standard-FPGA-board

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;


ENTITY Audio_Codec IS
PORT (
		--WM8731 pins = Pins benötigt für den Audio-Codec--
		AUD_BCLK	:	OUT	STD_ULOGIC; --Audio-Codec Bit-Stream Clock
		AUD_XCK		:	OUT	STD_ULOGIC; --Audio-Codec Chip Clock
		AUD_ADCLRCK	:	OUT	STD_ULOGIC; --Audio-Codec ADC LR Clock
		AUD_ADCDAT	:	IN	STD_ULOGIC; --Audio-Codec ADC Data
		AUD_DACLRCK	:	OUT	STD_ULOGIC; --Audio-Codec DAC LR Clock
		AUD_DACDAT	:	OUT	STD_ULOGIC; --Audio-Codec DAC Data
		
		
		--FPGA pins--
		clock_50		:	IN	STD_ULOGIC;	--50MHz Systemtakt
		key			:	IN	STD_ULOGIC; --Morsetaster
		reset			:	IN	STD_ULOGIC; --Reset-Signal
		FPGA_I2C_SCLK		:	OUT	STD_ULOGIC; --I²C-Taktsignal
		FPGA_I2C_SDAT		:	INOUT	STD_ULOGIC; --I²C-Datensignal
		enable			:	IN	STD_ULOGIC; --Switch Signal zum Umschalten zwischen dem Decoder und Encoder
		sound			:	IN	STD_ULOGIC; --Signal zum Anschalten des Tons bei einem codierten Morsesignal
		clock_12MHz_en		:	IN	STD_ULOGIC  --12MHz Taktsignal
		);

END Audio_Codec;





ARCHITECTURE structure OF Audio_Codec IS

TYPE State_type IS (reset_codec, slave, USB, Volume, power, interface, lineout, remove_mute, idle);
SIGNAL state	:	State_type	:=	reset_codec;
	
SIGNAL aud_mono:		STD_ULOGIC_VECTOR (31 DOWNTO 0)	:= (OTHERS => '0'); --Mono-Audiosignal
SIGNAL read_addr:		NATURAL RANGE 0 TO 94		:= 0;	--Anzahl der Bytes für einen Wellenzug eines 500Hz-Signals bei einer 48kHz Samplerate
SIGNAL ROM_ADDR:		STD_ULOGIC_VECTOR (6 DOWNTO 0);
SIGNAL ROM_OUT:			STD_ULOGIC_VECTOR (15 DOWNTO 0);

SIGNAL wM_i2c_busy:		STD_ULOGIC; 		--I²C ist noch beschäftigt
SIGNAL wM_i2c_done:		STD_ULOGIC; 		--I²C hat fertig übertragen
SIGNAL wM_i2c_send_flag:STD_ULOGIC; 			--Startkondition zur Übertragung des nächsten Datenwortes
SIGNAL wM_i2c_data:		STD_ULOGIC_VECTOR (15 DOWNTO 0); --I²C Daten
SIGNAL DA_CLR:			STD_ULOGIC; 		--Audio-Codec DAC Data


   COMPONENT Memory_System is
	  PORT (
			mem_clock_clk         : in  std_ulogic                     := 'X';             -- clk
			mem_slave_address     : in  std_ulogic_vector(6 downto 0)  := (others => 'X'); -- address
			mem_slave_debugaccess : in  std_ulogic                     := 'X';             -- debugaccess
			mem_slave_clken       : in  std_ulogic                     := 'X';             -- clken
			mem_slave_chipselect  : in  std_ulogic                     := 'X';             -- chipselect
			mem_slave_write       : in  std_ulogic                     := 'X';             -- write
			mem_slave_readdata    : out std_ulogic_vector(15 downto 0);                    -- readdata
			mem_slave_writedata   : in  std_ulogic_vector(15 downto 0) := (others => 'X'); -- writedata
			mem_slave_byteenable  : in  std_ulogic_vector(1 downto 0)  := (others => 'X'); -- byteenable
			mem_reset_reset       : in  std_ulogic                     := 'X';             -- reset
			mem_reset_reset_req   : in  std_ulogic                     := 'X'              -- reset_req
		);
    END COMPONENT Memory_System;



	COMPONENT Audio_generation IS
		PORT (
			aud_clock_12:		IN	STD_ULOGIC;
			aud_bk:			OUT	STD_ULOGIC;
			aud_dalr:		OUT	STD_ULOGIC;
			aud_dadat:		OUT	STD_ULOGIC;
			aud_data_in:		IN	STD_ULOGIC_VECTOR (31 DOWNTO 0)
		);
	END COMPONENT Audio_generation;
	 
	 
	 
	COMPONENT I2C IS
		PORT (
			i2c_busy:	OUT 	STD_ULOGIC;
			i2c_scl:	OUT 	STD_ULOGIC;
			i2c_send_flag:  IN	STD_ULOGIC;
			i2C_sda:        INOUT	STD_ULOGIC;
			i2c_addr:	IN	STD_ULOGIC_VECTOR (7 DOWNTO 0);
			i2c_done:	OUT	STD_ULOGIC;
			i2c_data:	IN	STD_ULOGIC_VECTOR (15 DOWNTO 0);
			i2c_clock_50:	IN	STD_ULOGIC
		);
	END COMPONENT I2C;

	
	
BEGIN


		audio:	COMPONENT Audio_Generation
						PORT MAP (
							aud_clock_12	=> clock_12MHz_en,
							aud_bk		=> AUD_BCLK,
							aud_dalr	=> DA_CLR,
							aud_dadat	=> AUD_DACDAT,
							aud_data_in	=> aud_mono
						);
	
	
		wm8731:	COMPONENT i2c
						PORT MAP(
							i2c_busy	=> wm_i2c_busy,
							i2c_scl		=> FPGA_I2C_SCLK,
							i2c_send_flag	=> wm_i2c_send_flag,
							i2c_sda		=> FPGA_I2C_SDAT,
							i2c_addr	=> "00110100",
							i2c_done	=> wm_i2c_done,
							i2c_data	=> wm_i2c_data,
							i2c_clock_50	=> clock_50
						);

		 Memory: COMPONENT Memory_System
					  PORT MAP (
							mem_clock_clk         => clock_12MHz_en,    -- mem_clock.clk
							mem_slave_address     => ROM_ADDR,     	    -- mem_slave.address
							mem_slave_debugaccess => '0', 		    --          .debugaccess
							mem_slave_clken       => '1',       	    --          .clken
							mem_slave_chipselect  => '1',  		    --          .chipselect
							mem_slave_write       => '0',       	    --          .write
							mem_slave_readdata    => ROM_OUT,    	    --          .readdata
							mem_slave_writedata   => (OTHERS => '0'),   --          .writedata
							mem_slave_byteenable  => "11",  	    --          .byteenable
							mem_reset_reset       => '0'	       	    -- mem_reset.reset
					  );
					  
		AUD_XCK 		<= clock_12MHz_en;
		
		AUD_DACLRCK <= DA_CLR;
		
		ROM_ADDR 	<= STD_ULOGIC_VECTOR(TO_UNSIGNED(read_addr,7));		
		
		
		-------------------------------------------------------------------------------------------------
		--Senden eines mono-Ausiosignals an die Entity "Audio_Generation" bei Betätigung der Morsetaste--
		--oder beim Erhalt eines codierten Morsesignals aus der Entity "Keyboard_Encoder"----------------
		-------------------------------------------------------------------------------------------------
Read_Audio_Data:	PROCESS (clock_12MHz_en, enable, reset, key, sound)	
		BEGIN	
			IF reset = '0' THEN
				read_addr <= 0;
				aud_mono <= (OTHERS => '0');
			
			ELSIF clock_12MHz_en'EVENT AND clock_12MHz_en = '1' THEN
				
				
					IF (key = '1' AND enable = '0') OR (sound = '0' AND enable = '1') THEN --reset
						read_addr <= 0;
						aud_mono <= (OTHERS => '0');
						
					ELSIF (key = '0' AND enable = '0') OR (sound = '1' AND enable = '1')THEN
					
						aud_mono(15 DOWNTO 0) <= ROM_OUT; --mono sound
						aud_mono(31 DOWNTO 16) <= ROM_OUT; 
						
							IF (DA_CLR = '1') THEN 
									
									IF (read_addr < 94) THEN
										read_addr <= read_addr + 1;
									ELSE
										read_addr <= 0;
									END IF;												
							END IF;						
					END IF;						
		END IF;			
	END PROCESS;