-- Dateiname: uart_rx
-- Design Software : Quartus II 13.0sp1 (64-bit)
--
-- Erstellt:
-- Bouchnak Wassim
-- Moujahid Bouhouch
-- Hier werden 4 Komponenten (uart_rx , uart_tx, 2*Binary_To_7Segment) instanziiert und miteinander verbunden
-- Die empfangene ASCII Zahl wird innerhalb der Prozessen „ token_generation “ und „ audio_sound “
-- zu morse enkodiert und zum AudioCodec übertragen.
-- 
--library ieee;
use ieee.std_logic_1164.all;
 
entity UART_Top is
 port (
 -- Main Clock (50 MHz)
 i_Clk : in std_logic;
 nrst : in std_logic;
 clockNC_en : in std_logic;
 i_UART_RX : in std_logic; -- UART RX Data
 
 i_UART_TX : out std_logic;
 tx_busy : out std_logic;
 uart_sound : out std_logic;
 
 
 
 -- Segment1 is upper digit, Segment2 is lower digit of 7 Segment Display
 o_Segment1_A : out std_logic;
 o_Segment1_B : out std_logic;
 o_Segment1_C : out std_logic;
 o_Segment1_D : out std_logic;
 o_Segment1_E : out std_logic;
 o_Segment1_F : out std_logic;
 o_Segment1_G : out std_logic;
 
 o_Segment2_A : out std_logic;
 o_Segment2_B : out std_logic;
 o_Segment2_C : out std_logic;
 o_Segment2_D : out std_logic;
 o_Segment2_E : out std_logic;
 o_Segment2_F : out std_logic;
 o_Segment2_G : out std_logic
 );
end entity UART_Top;
 
architecture RTL of UART_Top is
 
 signal w_RX_DV : std_logic;
 signal w_RX_Byte : std_logic_vector(7 downto 0);
 signal w_RX_DV_delayed : std_LOGIC;SIGNAL count : NATURAL := 0;
 SIGNAL token : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
 SIGNAL soft_reset_var : std_logic;
 signal w_Segment1_A, w_Segment2_A : std_logic;
 signal w_Segment1_B, w_Segment2_B : std_logic;
 signal w_Segment1_C, w_Segment2_C : std_logic;
 signal w_Segment1_D, w_Segment2_D : std_logic;
 signal w_Segment1_E, w_Segment2_E : std_logic;
 signal w_Segment1_F, w_Segment2_F : std_logic;
 signal w_Segment1_G, w_Segment2_G : std_logic;
 
 -- signal two_bits_count : NATURAL RANGE 0 TO 16 := 0;
 
 
 
 COMPONENT uart_rx is
 port (
 clk : in std_logic;
 nrst : in std_logic;
 rx : in std_logic;
 data : out std_logic_vector(7 downto 0);
 rx_dv : out std_logic
 );
 
 END COMPONENT uart_rx;
 
 
 COMPONENT uart_tx is
 port (
 clk : in std_logic;
 nrst : in std_logic;
 rx_dv : in std_logic;
 data : in std_logic_vector(7 downto 0);
 busy : out std_logic;
 tx : out std_logic
 );
 
 END COMPONENT uart_tx;COMPONENT Binary_To_7Segment is
 port (
 i_Clk : in std_logic;
 i_Binary_Num : in std_logic_vector(3 downto 0);
 o_Segment_A : out std_logic;
 o_Segment_B : out std_logic;
 o_Segment_C : out std_logic;
 o_Segment_D : out std_logic;
 o_Segment_E : out std_logic;
 o_Segment_F : out std_logic;
 o_Segment_G : out std_logic
 );
 
 END COMPONENT Binary_To_7Segment;
 
 
 
 
begin
 
 UART_RX_Inst : COMPONENT uart_rx 
 port map (
 clk => i_Clk,
 nrst => nrst ,
 rx => i_UART_RX,
 data => w_RX_Byte,
 rx_dv => w_RX_DV 
 );
 
 
 UART_TX_Inst : COMPONENT uart_tx 
 port map (
 clk => i_Clk,
 nrst => nrst ,
 rx_dv => w_RX_DV,
 data => w_RX_Byte,
 busy => tx_busy,
 tx => i_UART_TX 
 );
 
 SevenSeg1_Inst : COMPONENT Binary_To_7Segment
 port map (
 i_Clk => i_Clk,
 i_Binary_Num => w_RX_Byte(7 downto 4),
 o_Segment_A => w_Segment1_A,
 o_Segment_B => w_Segment1_B,
 o_Segment_C => w_Segment1_C,
 o_Segment_D => w_Segment1_D,
 o_Segment_E => w_Segment1_E,
 o_Segment_F => w_Segment1_F,
 o_Segment_G => w_Segment1_G
 );
 
 o_Segment1_A <= not w_Segment1_A;
 o_Segment1_B <= not w_Segment1_B;
 o_Segment1_C <= not w_Segment1_C;
 o_Segment1_D <= not w_Segment1_D;
 o_Segment1_E <= not w_Segment1_E;
 o_Segment1_F <= not w_Segment1_F;
 o_Segment1_G <= not w_Segment1_G;
 
 
 -- Binary to 7-Segment Converter for Lower Digit
 SevenSeg2_Inst : COMPONENT Binary_To_7Segment
 port map (
 i_Clk => i_Clk,
 i_Binary_Num => w_RX_Byte(3 downto 0),
 o_Segment_A => w_Segment2_A,
 o_Segment_B => w_Segment2_B,
 o_Segment_C => w_Segment2_C,
 o_Segment_D => w_Segment2_D,
 o_Segment_E => w_Segment2_E,
 o_Segment_F => w_Segment2_F,
 o_Segment_G => w_Segment2_G
 );
 
 o_Segment2_A <= not w_Segment2_A;
 o_Segment2_B <= not w_Segment2_B;
 o_Segment2_C <= not w_Segment2_C;
 o_Segment2_D <= not w_Segment2_D;
 o_Segment2_E <= not w_Segment2_E;
 o_Segment2_F <= not w_Segment2_F;
 o_Segment2_G <= not w_Segment2_G;
 
 
 token_generation: PROCESS (nrst, w_RX_DV)BEGINIF nrst = '0' THEN
 -- Initialisierung des Signals
 token <= (OTHERS => '0');
 
 ELSIF w_RX_DV'EVENT AND w_RX_DV = '1' THEN
 
 
 CASE w_RX_Byte IS
 
 --Buchstaben groß
 WHEN x"41" => token <="0000000000001101"; -- A
 WHEN x"42" => token <="0000000001010111"; -- B
 WHEN x"43" => token <="0000000001110111"; -- C
 WHEN x"44" => token <="0000000000010111"; -- D
 WHEN x"45" => token <="0000000000000001"; -- E
 WHEN x"46" => token <="0000000001110101"; -- F
 WHEN x"47" => token <="0000000000011111"; -- G
 WHEN x"48" => token <="0000000001010101"; -- H
 WHEN x"49" => token <="0000000000000101"; -- I
 WHEN x"4A" => token <="0000000011111101"; -- J
 WHEN x"4B" => token <="0000000000110111"; -- K
 WHEN x"4C" => token <="0000000001011101"; -- L
 WHEN x"4D" => token <="0000000000001111"; -- M
 WHEN x"4E" => token <="0000000000000111"; -- N
 WHEN x"4F" => token <="0000000000111111"; -- O
 WHEN x"50" => token <="0000000001111101"; -- P
 WHEN x"51" => token <="0000000011011111"; -- Q
 WHEN x"52" => token <="0000000000011101"; -- R
 WHEN x"53" => token <="0000000000010101"; -- S
 WHEN x"54" => token <="0000000000000011"; -- T
 WHEN x"55" => token <="0000000000110101"; -- U
 WHEN x"56" => token <="0000000011010101"; -- V
 WHEN x"57" => token <="0000000000111101"; -- W
 WHEN x"58" => token <="0000000011010111"; -- X
 WHEN x"59" => token <="0000000011110111"; -- Y
 WHEN x"5A" => token <="0000000001011111"; -- Z --Buchstaben klein
 WHEN x"61" => token <="0000000000001101"; -- a
 WHEN x"62" => token <="0000000001010111"; -- b
 WHEN x"63" => token <="0000000001110111"; -- c
 WHEN x"64" => token <="0000000000010111"; -- d
 WHEN x"65" => token <="0000000000000001"; -- e
 WHEN x"66" => token <="0000000001110101"; -- f
 WHEN x"67" => token <="0000000000011111"; -- g
 WHEN x"68" => token <="0000000001010101"; -- h
 WHEN x"69" => token <="0000000000000101"; -- i
 WHEN x"6A" => token <="0000000011111101"; -- j
 WHEN x"6B" => token <="0000000000110111"; -- k
 WHEN x"6C" => token <="0000000001011101"; -- l
 WHEN x"6D" => token <="0000000000001111"; -- m
 WHEN x"6E" => token <="0000000000000111"; -- n
 WHEN x"6F" => token <="0000000000111111"; -- o
 WHEN x"70" => token <="0000000001111101"; -- p
 WHEN x"71" => token <="0000000011011111"; -- q
 WHEN x"72" => token <="0000000000011101"; -- r
 WHEN x"73" => token <="0000000000010101"; -- s
 WHEN x"74" => token <="0000000000000011"; -- t
 WHEN x"75" => token <="0000000000110101"; -- u
 WHEN x"76" => token <="0000000011010101"; -- v
 WHEN x"77" => token <="0000000000111101"; -- W
 WHEN x"78" => token <="0000000011010111"; -- x
 WHEN x"79" => token <="0000000011110111"; -- y
 WHEN x"7A" => token <="0000000001011111"; -- z 
 
 --Zahlen
 WHEN x"30" => token <="0000001111111111"; -- 0
 WHEN x"31" => token <="0000001111111101"; -- 1
 WHEN x"32" => token <="0000001111110101"; -- 2
 WHEN x"33" => token <="0000001111010101"; -- 3
 WHEN x"34" => token <="0000001101010101"; -- 4
 WHEN x"35" => token <="0000000101010101"; -- 5
 WHEN x"36" => token <="0000000101010111"; -- 6
 WHEN x"37" => token <="0000000101011111"; -- 7
 WHEN x"38" => token <="0000000101111111"; -- 8
 WHEN x"39" => token <="0000000111111111"; -- 9
 
 --Sonderzeichen
 WHEN x"8E" => token <="0000000011011101"; -- Ä
 WHEN x"84" => token <="0000000011011101"; -- ä
 WHEN x"99" => token <="0000000001111111"; -- Ö
 WHEN x"9A" => token <="0000000011110101"; -- Ü
 WHEN x"81" => token <="0000000011110101"; -- ü
 WHEN x"E1" => token <="0101011111010101"; -- ß
 WHEN x"2D" => token <="0000110101010111"; -- -
 WHEN x"2E" => token <="0000110111011101"; -- .
 WHEN x"2C" => token <="0000111101011111"; -- ,
 WHEN x"2B" => token <="0000000111011101"; -- +
 WHEN x"22" => token <="1000000000000000"; -- " " 
 WHEN x"0A" => token <="1100000000000000"; -- "ENTER"
 
 WHEN OTHERS => token <= (OTHERS => '0'); 
 
 END CASE;
 
 END IF;END PROCESS; audio_sound: PROCESS(nrst,clockNC_en,w_RX_DV)VARIABLE two_bits_count : NATURAL RANGE 0 TO 16 := 0; BEGIN 
 
 
 
 IF nrst = '0' OR w_RX_DV = '1' THEN
 
 uart_sound <= '0';
 count <= 0;
 two_bits_count := 0;
  ELSIF clockNC_en'EVENT AND clockNC_en = '1' THEN

 IF two_bits_count >= 0 AND two_bits_count < 16 THEN
 
 --Codierung eines "Dits" als Signal mit doppelter Periodendauer der Wortgeschwindigkeit
 IF token(two_bits_count + 1 DOWNTO two_bits_count) = "01" THEN
 
 IF count >= 2 THEN
 count <= 0;
 uart_sound <= '0';
 two_bits_count := two_bits_count + 2;
 ELSE
 count <= count + 1;
 uart_sound <= '1';
 END IF;
 
 --Codierung eines "Dahs" als Signal mit sechsfacher Periodendauer der Wortgeschwindigkeit
 --(3-fache Dit-Länge)
 ELSIF token(two_bits_count +1 DOWNTO two_bits_count) = "11" THEN
 
 IF count >= 6 THEN
 count <= 0;
 uart_sound <= '0';
 two_bits_count := two_bits_count + 2;
 ELSE
 count <= count + 1;
 uart_sound <= '1';
 END IF;
 
 --Auslesen beenden, wenn nur noch Nullen im Token-Signal gelesen werden 
 ELSE
 
 uart_sound <= '0';
 two_bits_count := 16; 
 
 END IF;
 
 END IF;
 
 
 
 --Ist das Token-Signal komplett ausgelesen ausgabe_modusen und eine neue Taste wurde gedrückt,
 --dann soll das bitpaarweise Auslesen erneut beginnen
 --IF two_bits_count >= 16 THEN
 end if; END PROCESS;
end RTL;

 -- Dateiname: uart_rx
-- Design Software : Quartus II 13.0sp1 (64-bit)
--
-- Erstellt:
-- Bouchnak Wassim
-- 
--
-- UART-rx-Schnittstelle dient zum Empfangen von Daten über die Datenleitung rx.
-- der Empfänger berechnet den Takt des Senders und synchronisiert 
-- sich mit Hilfe der Start- und Stopbits darauf
--sobald ein datenpacket vollständig empfangen wird, wird das valid signal für nur 
--ein Taktzyklus um 1 gesetzt
--------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity uart_rx is
 port (
 clk : in std_logic; -- main clock 50Mhz
 nrst : in std_logic; --Reset
 rx : in std_logic; -- rx input
 data : out std_logic_vector(7 downto 0); --
 rx_dv : out std_logic -- impuls Signal wird um '1' gesetzt, sobald ein Datenpacket empfangen wird
 );
end uart_rx; 
 
architecture rtl of uart_rx is
 
 type statetyp is (START_erkennen, START, HALBES_BIT, DATA_simple, STOP);
 signal state : statetyp;
 
 -- CLK / baud rate --damit die dauer eines bit ermittelt wird
 constant clk_T_bit : natural := (50e6 / 115200); 
 
 -- Zum Zählen von Taktperioden
 signal clk_counter : integer range 0 to clk_T_bit - 1;
 
 -- Zum Zählen die Anzahl der übertragenen Bits
 signal bit_counter : integer range 0 to 7;
 
 -- Das um einen Taktzyklus verzögerte rx-Signal 
 signal rx_old : std_logic;
 
 signal data_reg : std_logic_vector(7 downto 0);
 
begin
 
 process(clk)
 begin
 if rising_edge(clk) then
 
 -- Pulsed
 rx_dv <= '0';
 
 rx_old <= rx;
 
 if nrst = '0' then
 data_reg <= (others => '0');
 data <= (others => '0');
 rx_dv <= '0';
 state <= START_erkennen;
 clk_counter <= 0;
 rx_old <= '0';
 bit_counter <= 0;
 
 
 else
 
 
 case state is
 
 -- Warten auf die fallende Flanke an rx
 when START_erkennen =>
 if rx_old = '1' and rx = '0' then
 state <= START;end if;
 
 -- warten auf die dauer eines bit
 when START =>
 if clk_counter = (clk_T_bit -2) then
 state <= HALBES_BIT;
 clk_counter <= 0;
 else
 clk_counter <= clk_counter + 1;
 end if;
 
 -- Warten auf die Dauer eines halben bits, um in der mitte des bits zu tasten.
 when HALBES_BIT =>
 if clk_counter = (clk_T_bit -1) / 2 then
 state <= DATA_simple;
 clk_counter <= (clk_T_bit -1); --clk_counter wird um den maximalen Wert gesetzt,
 else --damit das erste Bit im nächsten STATE direkt eingelesen wird
 clk_counter <= clk_counter + 1;
 end if;
 
 -- Sample all data bits
 when DATA_simple =>
 if clk_counter = (clk_T_bit -1) then
 clk_counter <= 0;
 
 -- die Daten werden von hohem zu niedrigem Index geschoben
 data_reg(7) <= rx;
 for i in 7 downto 1 loop
 data_reg(i - 1) <= data_reg(i);
 end loop;
 
 if bit_counter = 7 then
 state <= STOP;
 bit_counter <= 0;
 else
 bit_counter <= bit_counter + 1;
 end if;
 
 else
 clk_counter <= clk_counter + 1;
 end if;
 
 -- Warten auf die Dauer des stop-bits und zuweisung der Ausgangssignalen
 when STOP =>
 if clk_counter = (clk_T_bit -1) then
 state <= START_erkennen;
 data_reg <= (others => '0');
 data <= data_reg; 
 clk_counter <= 0;
 
 -- gibt an, ob ein Datenpacket vollständig empfangen Wurde
 if rx = '0' then
 rx_dv <= '0'; -- error
 elsif rx = '1' then 
 rx_dv <= '1'; -- ok
 else 
 rx_dv <= 'X'; --error
 end if;
 
 
 else
 clk_counter <= clk_counter + 1;
 end if;
 
 end case;
 
 end if;
 end if;
 end process; 
 
end rtl;

 

-- Dateiname: LCD_Controller
-- Design Software : Quartus II 13.0sp1 (64-bit)
--
-- Erstellt:
-- Bouchnak Wassim
-- 
--
-- UART-tx-Schnittstelle dient zum Senden von Daten über die Datenleitung tx
-- Die Daten werden als serieller digitaler Datenstrom mit einem fixen Rahmen übertragen,
-- der aus einem Start-Bit, acht Datenbits und einem Stopp-Bits besteht
-- die empfangenen Datenstrom in UART-RX werden zum Computer zurückgeschickt
--------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity uart_tx is
 port (
 clk : in std_logic;
 nrst : in std_logic;
 rx_dv : in std_logic;
 data : in std_logic_vector(7 downto 0);
 busy : out std_logic;
 tx : out std_logic
 );
end uart_tx; 
 
architecture rtl of uart_tx is
 
 -- CLK / baud rate --damit die dauer eines bit ermittelt wird
 constant clk_T_bit : natural := (50e6 / 115200); -- CLK / baud rate --damit die dauer eines bit ermittelt wird
 
 signal clk_counter : integer range 0 to clk_T_bit - 1;
 
 -- Zum Zählen der Anzahl der übertragenen Bits
 signal bit_counter : integer range 0 to 7;
 
 type statetyp is (IDLE, START, DATA_SENDEN, STOP);
 signal state : statetyp;
 
 -- Zur Abtastung der Dateneingabe
 signal data_sig : std_logic_vector(7 downto 0);
begin
 
 process(clk)
 
 begin
 if rising_edge(clk) then
 
 -- default value
 tx <= '1';
 busy <= '1';
 
 if nrst = '0' then
 state <= IDLE;
 busy <= '1';
 tx <= '1';
 bit_counter <= 0;
 data_sig <= (others => '0');
 else
 
 case state is
 
 -- warten auf das start signal
 when IDLE =>
 busy <= '0';
 
 if rx_dv = '1' then
 state <= START;
 data_sig <= data;
 busy <= '1';
 end if;
 
 -- das start bit senden
 when START =>
 tx <= '0';
 
 if clk_counter = clk_T_bit - 1 then
 clk_counter <= 0;
 state <= DATA_SENDEN;
 else
 clk_counter <= clk_counter + 1;
 
 end if;
 
 -- data bits senden
 when DATA_SENDEN =>
 tx <= data_sig(bit_counter);
 
 if clk_counter = clk_T_bit - 1 then
 clk_counter <= 0;
 
 if bit_counter = 7 then
 state <= STOP;
 bit_counter <= 0;
 else
 bit_counter <= bit_counter + 1;
 end if;
 
 else
 clk_counter <= clk_counter + 1;
 
 end if;
 -- stop bit senden
 when STOP =>
 if clk_counter = clk_T_bit - 1 then
 clk_counter <= 0;
 state <= IDLE;
 busy <= '0';
 else
 clk_counter <= clk_counter + 1;
 
 end if;
 
 end case;
 
 end if;
 end if;
 end process; 
 
end rtl;