--Angepasst von: https://github.com/AntonZero/WM8731-Audio-codec-on-DE10Standard-FPGA-board

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;


ENTITY Audio_generation IS
PORT (
	aud_clock_12:		IN		STD_ULOGIC;	--12MHz Taktsignal
	aud_bk:			OUT		STD_ULOGIC;	--ausgehendes 12MHz Taktsignal
	aud_dalr:		OUT		STD_ULOGIC;	--Audio-Codec ADC LR Clock
	aud_dadat:		OUT		STD_ULOGIC;	--Audio-Codec DAC Data
	aud_data_in:		IN		STD_ULOGIC_VECTOR (31 DOWNTO 0)	--32-Bit breites Mono-Signal aus der Entity "Audio-Codec"
);
END Audio_generation;


ARCHITECTURE structure OF Audio_generation IS

SIGNAL sample_flag:		STD_ULOGIC			:= '0';
SIGNAL data_index:		NATURAL RANGE 0 TO 31		:= 0;
SIGNAL da_data:			STD_ULOGIC_VECTOR (15 DOWNTO 0)	:= (OTHERS => '0');
SIGNAL da_data_out:		STD_ULOGIC_VECTOR (31 DOWNTO 0)	:= (OTHERS => '0');
SIGNAL aud_prscl:		NATURAL RANGE 0 TO 300		:= 0;
SIGNAL clk_en:			STD_ULOGIC			:= '0';


BEGIN

	aud_bk <= aud_clock_12;

	------------------------------------------------------
	--Sendet das Mono-Signal bitweise an den Audio-Codec--
	------------------------------------------------------
Generation:	PROCESS (aud_clock_12)
	
	BEGIN
	
		IF aud_clock_12'EVENT AND aud_clock_12 = '0' THEN
		
			aud_dalr <= clk_en;
			
			IF (aud_prscl < 250) THEN -- 48k sample rate
				aud_prscl <= aud_prscl + 1;
				clk_en <= '0';
			ELSE
				aud_prscl <= 0;
				da_data_out <= aud_data_in; -- get sample
				clk_en <= '1';
			END IF;
			
			
			
		IF (clk_en = '1') THEN --send new sample
			sample_flag <= '1';
			data_index <= 31;
		END IF;
		
		
		
		IF (sample_flag = '1') THEN
		
			IF (data_index > 0) THEN
				aud_dadat <= da_data_out(data_index);
				data_index <= data_index - 1;
			ELSE
				aud_dadat <= da_data_out(data_index);
				sample_flag <= '0';
			END IF;
			
		END IF;
	END IF;
	
END PROCESS;
END structure;