architecture arch of kb_code is
	constant BRK : std_ulogic_vector(7 downto 0) := "11110000";
	constant ENTER : std_ulogic_vector(7 downto 0) := "00010000";     
	constant BCKSPC : std_ulogic_vector(7 downto 0) := "01100110";
	constant UP_KEY : std_ulogic_vector(7 downto 0) := "01110101";		--x75
	constant DOWN_KEY: std_ulogic_vector(7 downto 0) := "01110010";	        --x72
	constant LEFT_KEY : std_ulogic_vector(7 downto 0) := "01101011";	--x6B
	constant RIGHT_KEY: std_ulogic_vector(7 downto 0) := "01110100"; 	--x74
	constant ESC_KEY	:std_ulogic_vector(7 downto 0) := "00010001"; 	--x11
	
	type statetype is(init, typematic, wait_brk, get_code, waste_cycle);
	signal state_reg, state_next : statetype;
	signal scan_out, w_data : std_ulogic_vector(7 downto 0);						
	signal compare_reg, compare_next : std_ulogic_vector(7 downto 0);
	signal scan_done_tick, got_code_tick : std_ulogic;	

.....

process(clk, reset)
	begin
		if reset = '1' then
			state_reg <= wait_brk;
			compare_reg <= (others => '0');
		elsif(clk'event and clk = '1') then
			state_reg <= state_next;
			compare_reg <= compare_next;
		end if;
	end process;
	
	process(state_reg, scan_done_tick, compare_reg, scan_out)
	begin
		got_code_tick <= '0';
		state_next <= state_reg;
		compare_next <= compare_reg;
		enter_tick <= '0';
		up_tick <= '0';
		down_tick <= '0';
		left_tick <= '0';
		right_tick <= '0';
		bck_spc_tick <= '0';
		esc_tick <= '0';
		
		if scan_done_tick ='1' then 	
			case scan_out is
				when BRK =>
				when ENTER =>
					enter_tick <='1';
				when BCKSPC =>
					bck_spc_tick <= '1';
				when LEFT_KEY =>
					left_tick <= '1';	
				when RIGHT_KEY =>
					right_tick <= '1';
				when DOWN_KEY =>
					down_tick <= '1';
				when UP_KEY =>
					up_tick <= '1';
				when ESC_KEY =>
					esc_tick <= '1';
				when others => 
					got_code_tick <= '1';
			end case;
		else 
		got_code_tick <= '0';
		enter_tick <= '0';
		up_tick <= '0';
		down_tick <= '0';
		left_tick <= '0';
		right_tick <= '0';
		bck_spc_tick <= '0';
		esc_tick <= '0';
		end if;		
		
	end process;
end arch;